Electronic circuit layout (ASIC) 2

I am an Electronics engineer, who has a lot of experience in Electronic circuit layout. I am very familiar with some tools (Cadence, and Synopsys) to draw layout for chip. Some circuit that I have done is NAND, OR, NOT XOR... Beside, my knowledge about the rule of CMOS Transistor is quite good. To be honest, I have a good communication (English IELTS 6.0) , so I am sure that I can fully understand your requirement. Please contact me . Thank you so much.

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