To complete this project I would implement the design in VHDL. Two primary design units would be needed: a serial decoder, and a PWM generator. Both units would contain parameterized values (generics in VHDL) for the duty cycle value/accuracy width and the number of channels.
I have working experience with VHDL, which has included PWM signal generation (for controlling system fan speed), and I have implement serial decoders in the past (SPI, I2C, and custom), so this project is well within my comfort zone.
My experience with FPGAs is primarily with Altera, so any guidance in that area would be in that direction.
Please contact me if you wish to discuss in further detail.