DLX CPU in VHDL - open to bidding

You will be using a modified DLX data path. The modifications are 1) The data path has removed the memory load/store elements 2) added a mux for both the S1 bus and S2 bus 3) The memory will be word addressable. Each instruction is not +4 difference but +1. Instr 0 is addr 0, Instr 1 is addr 1, etc. 4) The instructions to create are R-type: ADD, AND I-type: ADDI, ORI, XORI, SLTI, BEQZ 5) The BEQZ will not be adjusting the offset by 4 for bytes but just by 1. 6) S2op 7 is now const1 not const4 7) S2op only need pass, imm16sxt, imm16zxt, and const4 8) All the instructions are encoded the same way as we discussed in class. You will use the same ALUops but will only be creating the needed functions. You will be creating a VHDL module for registers, register file, mux, ALU, S2Modify (Performs the S2op), and memory. You will need to test each component independently. You FSM may need more steps to handle the rising edges of the registers. You will need to do some testing to see how it works. Testing run the following sequence of code 1) ADDI R1,R0,27 2) ORI R2,R0, 231 3) XORI R3,R1, 273 4) ADD R4,R2,R1 5) AND R5,R4,R2 6) Do a SLTI with one of your registers to get equal to zero 7) Do a BEQZ