ASYNCHRONOUS COMBINATION LOCK

This combination lock has a minimum sequence of four two-bit input symbols as the combination and appears to the user as if it is an asynchronous circuit. Actually, it is a synchronous circuit with a fast clock and synchronization of the user inputs. For a given input combination, the circuit goes to a state and cycles there until the input changes to a new symbol; thus, the combination cannot contain consecutive appearances of the same symbol. The lock is locked using an asynchronous RESET. a. Write a clear, complete specification for the function of your project system. You may use formal structures such as truth tables, state diagrams, ASMs, or register transfer language statements as necessary. b. Perform the design and enter the schematics. c. Devise a test plan for your design that will thoroughly test its function. d. Functionally simulate the design and debug it. Xilinx software is being used on this project with a motherboard demonstration. Upon creating the project, we use the following attributions => Family: Spartan3E, Device: XC3S100E, Package: CP132, Speed: -5, Synthesis Tool: XST (VHDL/Verilog), Simulator: ISE Simulator(VHDL/Verilog), Preferred Language: Verilog. If you need more information, feel free to contact with me. You will have to explain me the project! I also request you to be as simple and clear as possible! Thanks