I need VHDL Designer

In Progress Posted 2 years ago Paid on delivery

₹1500-12500 INR

Paid on delivery

In Progress Paid on delivery

This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch.

I am attaching the code that we have wrote for your reference.

We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2.

There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'.

From what I understood, the main issue is the interconnection between all the modules.

Electronics FPGA Microcontroller Verilog / VHDL

Project ID: #32325741

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2 proposals Remote project Active 2 years ago

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akifakkaya1's Profile Picture
akifakkaya1

I have 5 years practical experience in Digital System Design with VHDL and Verilog. I implemented different types IP cores and verified them. I also designed Simple Processors in my PhD period.

₹7777 INR in 10 days
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2 freelancers are bidding on average ₹10139 for this job

VLSIAkhi's Profile Picture
VLSIAkhi

Hi Client, I have Experince in Vlsi design and veriffication using Verilog and VHDL,My Team working on diffrent tools like Xilinx, Vivado, Modelsim, ect...... we working on Diffrent FPGAs like Basys3,Artix7, Spar More

₹12500 INR in 15 days
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