Verilog / VHDL jobs

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About Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    245 jobs found, pricing in CAD
    build a very simple MIPS code 6 days left

    I need a simple MIPS code. I will send you the task. I need it in an hour.

    Assembly C Programming C++ Programming Java Verilog / VHDL
    $26 (Avg Bid)
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    9 bids
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    FPGA Design and Asic 5 days left

    Hi there Please check the document

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $43 / hr (Avg Bid)
    $43 / hr Avg Bid
    7 bids
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    FPGA Design 5 days left

    Hi there Please check the document!

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $19400 (Avg Bid)
    $19400 Avg Bid
    6 bids
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    Floating Point on DSP48E1 5 days left

    I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you!

    FPGA Verilog / VHDL
    $301 (Avg Bid)
    $301 Avg Bid
    6 bids
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    MIPS Computer Design by Verilog HDL 4 days left
    VERIFIED

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    Assembly Digital Design Engineering FPGA Verilog / VHDL
    $171 (Avg Bid)
    $171 Avg Bid
    17 bids
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    need to implement an ieee paper using verilog or vhdl. -- 2 4 days left

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    Verilog / VHDL
    $158 (Avg Bid)
    $158 Avg Bid
    7 bids
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    200418_Verilog 4 days left
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    Electrical Engineering Electronics Verilog / VHDL
    $64 - $102
    Sealed
    $64 - $102
    4 bids
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    Conceive SDR GnuRadio blocs 4 days left
    VERIFIED

    This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send...

    Electrical Engineering Electronics Linux Microcontroller Verilog / VHDL
    $893 (Avg Bid)
    $893 Avg Bid
    4 bids
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    Implementing Bit stuffing in verilog 3 days left

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    $40 (Avg Bid)
    $40 Avg Bid
    9 bids
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    Edge detection by using laplacian 3 days left

    I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co...

    C Programming C++ Programming CUDA Software Architecture Verilog / VHDL
    $189 (Avg Bid)
    $189 Avg Bid
    1 bids
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    Sending and receiving tcpip xgmii packets over SFP+ 3 days left
    VERIFIED

    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    FPGA Verilog / VHDL
    $594 (Avg Bid)
    $594 Avg Bid
    4 bids
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    plc program and hmi design Simulation 3 days left

    I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    $24 (Avg Bid)
    $24 Avg Bid
    14 bids
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    develop Simple SW to write on the IC Card/Server 3 days left

    I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i...

    C Programming Electronics Microcontroller PCB Layout Verilog / VHDL
    $363 (Avg Bid)
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    4 bids
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    translate C++ code in systemc. 3 days left

    translate c++ code in systemc and implement constrained random verification methodology.

    C Programming C++ Programming Software Architecture Verilog / VHDL Very-large-scale integration (VLSI)
    $34 (Avg Bid)
    $34 Avg Bid
    4 bids
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    build a software 3 days left

    translate c++ code in systemc. and implement constrained random varification methodology.

    C++ Programming Software Architecture Verilog / VHDL Very-large-scale integration (VLSI)
    $55 (Avg Bid)
    $55 Avg Bid
    2 bids
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    Create a DLX Data Path Using VHDL 2 days left

    Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

    Assembly FPGA Microcontroller Software Architecture Verilog / VHDL
    $227 (Avg Bid)
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    8 bids
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    build a software 2 days left

    translate a C++ code in systemc module.

    C Programming C++ Programming Verilog / VHDL
    $40 (Avg Bid)
    $40 Avg Bid
    3 bids
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    convert the C++ language code in systemc. 2 days left

    you have to translate C++ code in systemc language.

    C Programming C++ Programming Software Architecture Verilog / VHDL
    $42 (Avg Bid)
    $42 Avg Bid
    3 bids
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    Do VHDL project on the ModelSim 2 days left
    VERIFIED

    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $195 (Avg Bid)
    $195 Avg Bid
    11 bids
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    SoundLocator 2 days left

    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

    Android Electronics FPGA Java Verilog / VHDL
    $791 (Avg Bid)
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    14 bids
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