Verilog / VHDL Jobs

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Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

7 jobs found, pricing in CAD

VHDL, FPGA, VGA 4 days left

Hi I'm looking for a good vhdl programmer to help me with a code. I'm supposed to bring in a simple logo, then i,m supposed to be able to display the logo on the center of a screen(using a vga connection) and my name on the bottom left corner while being able to flip the logo with a button on my fpga board the deadline is thursday. thank you. I have the initial codes. I'll provide m...

$82 (Avg Bid)

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Dice game on Quartus II 4 days left

I have a project coming up ‪in less than 12 hours‬. I would appreciate if you can help me individually in doing the project in anyway at a deal that shall satisfy your effort. please take a look at the instructions and let me know if you can help: You will use the Altera DE2-115 board (Side note: you only need to design the software and I will install it to the board myself), Quartus II software ...

C Programming C++ Programming Electronics Microcontroller Verilog / VHDL

$368 (Avg Bid)

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10 bids

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Simple CheckSum Program 4 days left

Create an Adler-32 offload engine. As part of a larger system a required will be a provided resource to compute the Adler-32 checksum on data being sent to you a byte at a time.

C Programming Digital Design Logo Design Verilog / VHDL

$78 (Avg Bid)

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1ns Bin Size Histogrammer, FPGA + ADC 3 days left

I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns. I need a system to histogram the time between all adjacent pulses' rising edges, that each bin of the histogram is 1ns wide. For example, starting from t=0, if the input signal has rising edge...

Electrical Engineering Electronics FPGA Verilog / VHDL

$1431 (Avg Bid)

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wireless body area sensor node protocol 3 days left

My project require someone knowledgable in the area of wsn. The main Idea would be enhancing a currently existing routing protocol in wireless sensor nodes, the code can be done in any language, I prefer Matlab and or c++ using omnet++ simulator

C Programming C++ Programming Electrical Engineering Matlab and Mathematica Verilog / VHDL

$1583 (Avg Bid)

$1583 Avg Bid

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z7010 DMA Controller Red pitaya 21 hours left

Hello i am working on red pitaya board which has z7010, and i need help with DMA controller. I have troubles managing data transfer between AXI Stream IP and DDR memory. The project is setuped completely the application is also written. but its not working as supposed to. The thing i need from freelancer is that you need to debug the design an c code, i ame sure minute changes are required. onl...

Digital Design FPGA Verilog / VHDL

$27 (Avg Bid)

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2 bids

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VLSI work.. 2 hours left

Design and analyze different MOS combinational logic circuits

Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL

$40 (Avg Bid)

$40 Avg Bid

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