Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    11 jobs found, pricing in CAD
    VHDL Firmware Expert needed 6 days left
    VERIFIED

    I've FPGA based ADC/DAC board. Currently I'm looking for an VHDL expert using Altera(intelFPGA) tool. Please share your experience in the proposal. Which FPGA chip did you use before?

    $1354 (Avg Bid)
    $1354 Avg Bid
    9 bids
    optical communication help 6 days left
    VERIFIED

    OPTIWAVE design a Radio-over-Fiber System Analyse your system performance,implement the system in Optiwave and analyse its performance.

    $127 (Avg Bid)
    $127 Avg Bid
    7 bids

    more details will be given in the chat

    $68 (Avg Bid)
    $68 Avg Bid
    2 bids
    Logisim project 4 days left

    In this project you will implement a modified hangman game machine with Logisim. For the game, the minimum requirements are as follows: 1. The word is taken as 64-bit input. 2. Each 8 bit refers to the ascii code of a character. Therefore, the word is 8 characters at most. For instance “hello” is represented as: 00000000 00000000 00000000 01101000 01100101 01101100 01101100 01101111 3....

    $115 (Avg Bid)
    $115 Avg Bid
    5 bids

    I need a creative person in Fuzzy Logic System

    $23 (Avg Bid)
    $23 Avg Bid
    8 bids

    immediately required Verilog and Matlab programmer to solve a problem. I will pay 250/ hour.

    $4 / hr (Avg Bid)
    $4 / hr Avg Bid
    12 bids

    I want to learn how to design a double loop controller mathematically and study the stability for boost converter

    $61 (Avg Bid)
    $61 Avg Bid
    8 bids

    Proficient in System Verilog/UVM/OVM, OOP/C++ • GPU, or Memory System • code coverage and functional coverage driven verification methodology • creating, running and debugging of SystemVerilog/UVM constraint-random Testbench

    $8 / hr (Avg Bid)
    $8 / hr Avg Bid
    11 bids

    Multiplier using System verilog

    $18 (Avg Bid)
    $18 Avg Bid
    9 bids

    I NEED someone to correct about 13 errors in some verilog questions contact me i will send u files

    $32 (Avg Bid)
    $32 Avg Bid
    20 bids