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prior lake, united states
It's currently 6:16 AM here
Joined October 23, 2008
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vw7069422vw
@vw7069422vw
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prior lake, united states
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Senior ASIC Design Engineer
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Experience
Senior ASIC Deisgn Engineer
Feb 2012 - Present
Designed SRAMs for harsh environments. Designed and simulated a DLL and DDR2 memory interface.
ASIC Design Engineer
Jun 2009 - Feb 2012 (2 years, 8 months)
Responsible for ASIC physical design of many blocks - from very small to several million gates.
ASIC Design Engineer
May 1998 - Jun 2009 (11 years, 1 month)
ASIC design (logic design, physical design, methodology) and memory design.
Education
Electrical Engineering
(5 years)
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