Dear sir,
I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, DC Compiler, ICC and others.
I have done Wallace Tree multiplier with testbench before on Vivado and generated its bitsream file. Please check the review below:
https://www.freelancer.com/projects/verilog-vhdl/bit-multiplier/reviews
Wallace tree multiplier is one of the fastest multipliers in CMOS technology. Also, the Verilog code is parametrized, so it can fit 16 bits multiplier, too.
In addition, I have done other large projects such as CNN hardware acceleration on FPGA in Verilog language.
Please contact me to discuss more about this project.
Kindest regards.