Filter bank Simulink and VHDL implementation

£20-250 GBP

Closed

Posted

over 5 years ago

£20-250 GBP

Paid on delivery

My aim of this work is to see how it would be done from a different point of view. What I would like to be done is: * Check the Simulink model to see if that's done correctly. * Finish minimum resource version in filter bank Simulink model (just add memory and switch between memory in each cycle and do DFT). * Implement the minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator. * Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT. * Do a bit-true simulation in order to confirm that VHDL model works the same as the Simulink minimum resource version. Filter bank specification is given in [login to view URL] file Number of users: 4 Sampling frequency: 16kHz

Electrical Engineering

Engineering

FPGA

Matlab and Mathematica

Verilog / VHDL

Project ID: 18292582

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4 proposals

Remote project

Active 5 yrs ago

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@ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using FPGA please message me so that we can discuss

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@thasleemkamila

I have well experienced in doing such kind of jobs...........................................................................................

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@schoudhary1553

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£150 GBP in 3 days