Analog circuit design using cadence
₹12500-37500 INR
Paid on delivery
The circuit for DLL is to be designed at transistor level using CMOS technology and implemented in the 130 nm AMS process technology. The aim is to achieve a design with dynamic range of 50ns, jitter of less than 10ps and a time granularity of 100ps.
Project ID: #26381051
About the project
5 freelancers are bidding on average ₹20000 for this job
I have well experienced in doing such kind of jobs....................................................................................
Hi I am an electronics engineer I can do this task for you feel free to contact me.
I have done many projects in serdes and hence will be able to do this as well Relevant Skills and Experience I have made complete serializer in 28nm FDSOI. I have also worked on projects like PLL and dll