Implementing an Image Processing project on Zynq Device on a custom FPGA using the tools by Xilinx(Vivado HLS, IDE and SDK)

The project I’m working on is called Dust Detection on Reed Switch Images. The project is implemented on the Zynq device on a custom FPGA development board. The first half of the algorithm is implemented on the PL side (using Vivado HLS and IDE) and the second half of the project is to be implemented on the PS side of the Zynq device (using Xilinx SDK). The steps that are to be implemented on the PL part of the project are complete and desired outputs are obtained. A gist of the PL part of the project: The HLS IP core is created on Vivado HLS and then exported to Vivado IDE. The input image is stored in an input VDMA (with only read channels enabled) which is connected to the input of the HLS IP, and the output of the HLS IP is given to an output VDMA (with only write channels enabled). The design steps such as synthesis, implementation, and bit-stream generation are carried out on IDE and the hardware is exported to SDK. We then create an application project on SDK and run the application project on hardware connected by restoring and dumping images across the input and output VDMA addresses. The output of the PL part of the project is obtained across the output VDMA address. The second half of the project involves taking the PL output from the output VDMA and using it for carrying out the remaining steps of the algorithm on the PS side i.e., on SDK. I need help with: (1) How the PL output is used for further processing on the PS side and (2) Codes to Implement the last 3 algorithm steps of the algorithm on PS. From the algorithm attached below, all steps until Negate the dilated image are complete and I need help with the codes for the next 3 steps that are to be implemented on SDK.