Hi,
-FPGA design engineer since last 7 years
-Expertise in verilog/VHDL
Please find below details of the projects
TSMAC Hardware acceleration(3months)
The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction.
CSI-2 transmitter and receiver(6months)
The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards
eMMC Host Controller and Device controller(3months)
The project is to develop eMMC host and Device controller IP according to the JEDEC standards.
Mobile camera–testing(3months)
The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies
High resolution camera(6.5months)
The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor
-Test project for DDR2 accesses
-Development of calibration module
-Development of chain control module
-Development of control signal generator
-Development of Generic LUT module
-Development of Divider radix-2 algorithm
-Development of atan calculator
-Development of MCB reader state machine
Color Pipeline(15months)
The project is to develop 2D and 3D image processing algorithms on Aptina sensor
-Development of Generic Frame Buffer pCore
-Development of data compression and data packing pCore
-Development of data packing pCore
Video Processing Unit(13 months)
-Improvement in algorithms to reduce FPGA resource utilization and decrease latency
Hello sir,
I am a hardware engineer. I've done many projects on IP core using Verilog.
It would be my pleasure to work on your project. Please contact me to discuss the details.
Thank you for your consideration
