Coding in SystemVerilog and UVM
$750-1500 USD / hour
Occasional Verilog or System Verilog code writing. For example, monitors, drivers, agents or small testbenches
Project ID: #4175263
About the project
13 freelancers are bidding on average $850/hour for this job
Dear sir, I have more than 5 years experience in hdl programming and testbench writing
Hi, Highly experienced in SV and UVM methodology for vetification. Lets discuss the project... More on PM.
Creo que puedo ayudarte. Estudio ingenieria electronica y he programado varias FPGA en VHDL para diferentes trabajos. Espero que me contactes.
Hi, I have more then 1.5 year experience in System Verilog as well in methodology like UVM,OVM. Can do it very easily. Give me your requirement.
I'm an senior electronic engineer with more than seven years of experience working with FPGAs, HDLs, Digital Design, DSP, embedded, ... I have worked as a R&D engineer designing equipment for RF microwave using soft More
The great works for me. I learned it in the univercity and I like this coding time-by-time,
i have good expertise in chip verification. i am very comfortable with languages like verilog, system verilog. looking forward to hear from you soon :)
Have 12+ years of experience in handling Verilog/ System Verilog Verification testbench development . Can I be of any help here ?