(30 points) Show the layout of the specified cache for a CPU that can address 8M x 16 of memory. Give the layout of the bits per location and the total number of locations.
(Hint: Similar to Self-Assessment Question 6 and Discussion Topic 9)
a) The cache holds 128K x 16 of data and has the fully associative strategy
b) The cache holds 128K x 16 of data and has the direct mapped strategy
c) The cache holds 128K x 16 of data and has the two-way set-associative strategy