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    1,645 vhdl project vhdl project jobs found, pricing in CAD

    Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge

    $21 / hr (Avg Bid)
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    help in VHDL codes ,, everything will be explained later

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    je suis suposé faire un projet en VHDL de A jusqu'à Z , je manipule bien le logiciel je peux decrire aussi que simuler et implémenter sur une carte FRGA , mais je me crois pas au niveau pour bien choisir un sujet ( je suis débutant , je connais pastrop sur ce que peut faire ce merveilleux logiciel ) aussi que faire l'architecture globale du projet

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    Prelab Ended

    Write VHDL code

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    have few questions on digital circuits that I need help with. will provide more details of interested

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    VHDL CODE MATLAB DESIGN MATHEMATICAL NEED

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    We need to develop a code for Fifo router, crossbar switch and cdma router using verilog or vhdl language on cadence platform. The required details are shared in the paper attached.

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    write VHDL codes to generate the following chaotic system (1)henon map 2d (2) lorenz system 3d you will need to using fixed point representation in your vhdl codes.

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    I would like to work with a guy how can write hardware description in vhdl of a multiplier based on redundant binary representation. To prove his ability and skills, the freelancer has to provide a description of RBSD(Redundant Binary Signed Digit) Adder More work in this space is to come, we're looking for a long term partnership with the chosen freelancer

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    VHDL programm plus testbenches

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    VHDL code design

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    hi i would like to convert a simple code from matlab to vhdl

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    Details in chat, contact me for more if interested.

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    Setup a fpga (ALTRA MAX3000A) or similar as an SPI slave and capture the channel frequency TX and RX data to a silicon systems si4464 by monitering MISO MOSI clock and Enable RX MOSI 0x77 followed by MISO up to 8 bytes containing the received data TX MOSI 0x66 followed by MOSI up to 8 bytes containing the Transmit data Frequency set MOSI 0x11 0x40 next byte is the number of bytes typically...

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    I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms and matlab

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    Design of Arithamatic and logic unit using VHDL

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    I need to implement cordic algorithms in VHDL

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    The purpose of the Pattern Generator is to generate video stream with specific image for test purpose of backend device. Design in VHDL Only experienced freelancers with positive record See attached document for more information Please contact me for questions

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    The purpose of the switch is to switch video stream of Altera's VIP protocol from any input to any output. Each output can receive only one stream at a time. One input can be broadcasted to multiple outputs. Detailed requirements document attached. Only experienced freelancers with reviews

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    please check the attached file . I want to complete using quartus tool to install it on fpga altera kit in 3 hrs max

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    i am looking for the VHDL or Verilog code that have UDP or TCP protocol and can have Lan connection fpga spartan 6 to pc by wiznet W 5300 . anyone can help me for that?

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    ...compressed data will be send over GigE and/or USB 3.0. I'm a PCB designer with RF design experience, for this project: 1. Propose design architecture ( Pure FPGA, FPGA+controller, DSP or SoC FPGA etc.) 2. PCB Design 3. Software or VHDL project You can quote for total or for each parts.I can design and verify second part myself if it is needed.

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    it has to print it in HIX in the digital numbers of the bored max voltage is 3.3 should be print as 3FF because we r working in 10 bits

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    it has to print it in HIX in the digital numbers of the bored max voltage is 3.3 should be print as 3FF because we r working in 10 bits

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    it has to print it in HIX in the digital numbers of the bored max voltage is 3.3 should be print as 3FF because we r working in 10 bits

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    I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms

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    I have an assignment that my lecturer asked me to do and the deadline is 28/7/2017. I need to show him the simulation that the program is running and may be few basic question. I want someone to do the assignment and show me how I have to show to my teacher that the program is running (simulation). I have attached a file where there is 3 question. But I only need to solve question 2. That is "...

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    I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms

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    Mirror unit receives data stream via Avalon ST interface which is buffered and processed if necessary. Each steam starts with Control packet which contains description about the image like interlacing, width and height or definition of the data received (Altera's VIP has it's own protocol, it is assumed that you familiar with it). Please read attached document for more detailed descr...

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    I need you to develop some software for me. I would like this software to be developed . Alu/register file in vhdl

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    Digital down converter , Digital Up converter VHDL & Matlab . DDC: 1- Fsample : 16 bit x 400 MSPS Max. 2- Bandwidth : programmable from 100Khz to 20Mhz. 3- IF Tuner : programmable from DC to 100Mhz , resolution 0.5Hz . 4- DDC decimation Range : 8 to 4096 . 5- CFIR : programmable 20 taps( 18 bit coefficient ) . 6-

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    Estimation of Power of an FPGA by using complex VHDL codes is the main task of the project, I need help with the VHDL .

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    I am looking for developer for digital signal Processing , I need VHDL code for : 1- Digital Up converter . 2- Digital Down Converter . 3- SSB , LSB , USB , ISB Modulation / demodulation . 4- AME Modulation/ demodulation 5- FM Modulation/ demodulation . 6- FSK Modulation/ demodulation 7- GMSK Modulation/ demodulation 8- QAM Modulation/ demodulation

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    sequence ending in 1110010101 design both mealy and moore machine and than test and compare their function using MAX PLUS II package on Quartus II

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    Hello, I need the implementation and simulation of...I need the implementation and simulation of the FFT (Fast Fourier transformer) of the following points: 8 points, 16 points, 32,64, 128, 512 points, 1024 and 2048 points, in VHDl the program must be synthesizable With xilinix ise design software The results of the consumption slices must appear...

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    Implementation of Image processing algorithms on FPGA/CPLD hardware using VHDL, and Verilog, MATLAB

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    VHDL expert required for a simple task. More details via pm

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    The objective of my project is to implement the Viola-Jones algorithm to detect the number of faces in an input image on FPGA by using VHDL. The input image is saved in BRAM and i need to process the image and detect the total number of faces in that image. The detected faces will be surrounded by the square/rectangle.

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    The objective of my project is to implement the Viola-Jones algorithm to detect the number of faces in an input image on FPGA by using VHDL. The input image is saved in BRAM and i need to process the image and detect the total number of faces in that image. The detected faces will be surrounded by the square/rectangle.

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    The objective of my project is to implement the Viola-Jones algorithm to detect the number of faces in an input image on FPGA by using VHDL. The input image is saved in BRAM and i need to process the image and detect the total number of faces in that image. The detected faces will be surrounded by the square/rectangle.

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    I am looking for a freelancer to help me with my project. The skills required are FPGA, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

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    Implementar um jogo em verilog ou vhdl em vga

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    Implement algorithms in Xilinx FPGA writing Verilog / VHDL code to generate optimize RTL and create software to test and characterize the algorithms.

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    I am looking for a freelancer to help me with my project. The skills required are Matlab and Mathematica, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.

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    matlab Ended

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.

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    ...freelancer to help me with my project. The skills required are FPGA, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files. and also i am searching for phd project if you have any problem with solution

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    Segue trabalho em anexo

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    Need Embedded Designer Who has Excellent skills in ARM/AVR C/C+, Embedded c programing for designing a hardware module for an agricultural product. Verilog and VHDL are Added Advantage

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    I need someone to make some change to some VHDL code.

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