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  • Hire     kundanvaghela
Hire     kundanvaghela

    kundanvaghela kundanvaghela

    India $10 USD / hour
    ASIC/FPGA/SoC design and verificaion engineer
    India
    2.3
    1 review 1 review $10 USD per hour
    71% FOR ON TIME AND ON BUDGET IS NOT RIGHT..... hi i have done more than 20 projects on UVM,systemverilog and verilog , VHDL you can see some big projects below, 1s FUNCTIONAL VERIFICATION OF UNIVERSAL MEMORY CONTROLLER:- Description: Universal memory controller supports a variety of memory devices, 8 Chip selects,...
    71% FOR ON TIME AND ON BUDGET IS NOT RIGHT..... hi i have done more than 20 projects on UVM,systemverilog and verilog , VHDL you can see some big projects below, 1s FUNCTIONAL VERIFICATION OF UNIVERSAL MEMORY CONTROLLER:- Description: Universal memory controller supports a variety of memory devices, 8 Chip selects, each uniquely programmable. SDRAM,SSRAM, FLASH, ROM and many other devices supported. It has feature like Burst transfers and burst termination Industry standard WISHBONE SoC host interface Responsibilities: Analysis of the specification document. Listing down feature. Developing test plan. Template environment coding of test-bench architecture. Coding test-bench component and integration of them. Connect different types of memory like SRAM.SDRAM, and FLASH to DUT. Developing sanity test cases and functional test cases. Functional and code coverage Setting up regression and verification closure HVL:- System Verilog Tool:- Questa sim 10.4e 2nd AHB Interconnect Functional Verification using UVM & System Verilog Test plan development Developing test bench architecture Verification closure using Functional coverage & code coverage as closing criteria. Methodology: UVM 3rd Development of AXI 3.0 VIP and validation using AXI slave VIP Description: AXI interconnect is configurable design for connecting multiple masters to multiple slaves. Design also has a configuration interface for configuring slave address ranges. As part of design verification we verified interconnect for different number of masters, slaves and slave address range configurations. Responsibilities: Test plan development TECHNICAL SKILL Developing test bench architecture coding Verification closure using Functional coverage and Code coverage as closing criteria HVL:- System Verilog Tool:- Questa sim 10.4e skills; Digital design UVM SystemC System Verilog Verilog VHDL UNIX scripting PERL less
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  • Hire     ArqOrozco
Hire     ArqOrozco

    ArqOrozco ArqOrozco

    Mexico $15 USD / hour
    Arquitecto y Artista Visual
    Mexico
    0.7
    1 review 1 review $15 USD per hour
    Arquitecto dedicado a la Visualización Arquitectónica 3D para proyectos y Desarrollos Comerciales, Habitacionales y Urbanísticos. Mobiliario y diseño de interiores. Renders, Fotomontajes y Animaciones. -------------------------------------------------------------------------------------------------------------------...
    Arquitecto dedicado a la Visualización Arquitectónica 3D para proyectos y Desarrollos Comerciales, Habitacionales y Urbanísticos. Mobiliario y diseño de interiores. Renders, Fotomontajes y Animaciones. ------------------------------------------------------------------------------------------------------------------------------------- Architect dedicated to 3D Architectural Visualization for projects and Commercial, Residential and Urban Development. Furniture and interior design. Renders, Photomontages and Animations. less
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